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Altera_Forum
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17 years ago

Stratix II PLL and crossing clock domains

Hi, I want to transfer data between two clock domains(12 MHz to 20 MHz). I am using a Stratix II FPGA PLL to generate both clocks from a 100 MHz clock. I need that the first rising...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Your 2 clocks will have coincident edges every 15th clock of the 12MHz domain and every 30th clock of the 20MHz domain.

Your task therefore would be to determine when this coincidence occurs using a phase detector of your own design. You would then provide a clock enable in each of the domains on the clock cycle prior to the coincident edge.

I have no idea how you could constrain your timing so that the analyzer wouldn't flag a timing violation. I usually set false paths between clock domains and design the logic so as to avoid a violation.

This is not a standard way to cross clock domains. Have you considered using a dual-clock FIFO?

Jake