Stratix II GX Transceiver (basic) test design

Question

Hi,

I have a problem to get the Stratix II gx-Transceivers to run. My test-design uses a data-generator which produces a 32bit binary counter in a frequency of 100 MHz (from a PLL). I connected this bus to a ALT2GXB-component with the following configuration:

- protocol: basic, no loopback

- op-mode: receiver and transmitter

- deserializer block width: double, channel width 32 bit

- input clock frequency 100 mhz / 4000 Mbps, rate division factor 1

- pll: train receiver PLL from pll_inclk

- no calibration block

- no byte ordering block

- no 8b/10b decoder/encoder

- word alignment pattern: 11101100

- create pattern detect output

I use the Stratix II GX PCIe-Development-Board with an optical Transceiver in the SFP Port. I connected the SFP-TX with the SFP-RX via an optical wire. The goal is to show the most significant bits (31 downto 24) of my counter on the user-LEDs. Instead, I see wild things I can't value. When I remove the cable, the LEDs don't blink further. The least significant bits of the counter (7 downto 0) are replaced with the constand pattern I entered in the "word alignment pattern"-field of alt2gxb-megawizard. The pll_inclk is fed by the sfp_refclk Port. RX and TX-PLLs are locked. All unused pins are driven as input-tri-stated.

Has anyone an idea how to get this project work?

altera_forum · Answer

The problem is solved. But another one has risen....

First the soulution:

For other reasons, I had to change the frequency of my design from 100 to 120 MHz with 8b/10b coding. The data rate of the transceiver then has to be 3840 Mbps. This is the value which is to fill in the alt2gxb-megawizard field.

Additionally, there must be enough free space for 8b/10b-coding which comes on top. the "real" data rate should be 4800 Mbps. Furthermore, I measured this with a serial data analyzer. The measured rate was 4976 Mbps, which is a multiple of my gxb reference clock of 155.52 MHz.

The new problem is that I can see my data only after some reset-signals. For that problem I am going to open a new thread.

altera_forum · Answer

hi DN2009, I was wondering; how did you manage to get your PLL to use the 155.52MHz signal? My design refuses to compile, saying that the voltage level is wrong. This is the error i get :

Pin P7 does not support I/O standard 3.3-V LVTTL

Can you tell me why? Thanks. I have the exact same board as you.

altera_forum · Answer

hi,

you must set the voltage standard to LVDS. this is because the clock signal is a differential pair signal (Low Voltage Differential Signal or so) and uses two pins of the fpga, one positive and one negative. If you select lvds, quartus II should automatically assign the negative pin P8.

Daniel

altera_forum · Answer

Hey thanks. The manual is very unclear about this. Altera documentation is poor.

By default Quartus assigns all pins for the board as 3.3V.

Another issue you might be interested in : Do you know that 100Mhz signal is pin A20/A21 LVDS? Yeah, its not in the crappy manual.

Thanks for the help.

altera_forum · Answer

Hey,

I know I am a little late with this, but I am trying to do EXACTLY what you guys discussed here.

I've been sitting on this for weeks, trying any tip and trick i could find and I am not getting anywhere.

If any of you is seeing this, would it be possible to send me a working example?

I would appreciate any kind of help.

Max

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Stratix II GX Transceiver (basic) test design

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