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Altera_Forum
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16 years ago

Stratix II GX Transceiver (basic) test design

Hi, I have a problem to get the Stratix II gx-Transceivers to run. My test-design uses a data-generator which produces a 32bit binary counter in a frequency of 100 MHz (from a PLL). I connected th...
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Altera_Forum
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16 years ago

hi,

you must set the voltage standard to LVDS. this is because the clock signal is a differential pair signal (Low Voltage Differential Signal or so) and uses two pins of the fpga, one positive and one negative. If you select lvds, quartus II should automatically assign the negative pin P8.

Daniel