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Altera_Forum
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16 years ago

Stratix II GX Transceiver (basic) test design

Hi, I have a problem to get the Stratix II gx-Transceivers to run. My test-design uses a data-generator which produces a 32bit binary counter in a frequency of 100 MHz (from a PLL). I connected th...
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Altera_Forum
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16 years ago

hi DN2009, I was wondering; how did you manage to get your PLL to use the 155.52MHz signal? My design refuses to compile, saying that the voltage level is wrong. This is the error i get :

Pin P7 does not support I/O standard 3.3-V LVTTL

Can you tell me why? Thanks. I have the exact same board as you.