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tony_yu's avatar
tony_yu
Icon for New Contributor rankNew Contributor
4 years ago

Stratix II EP2S90F1020 JTAG issue

Dear Intel Employee, I have a Stratix II EP2S90F1020 FPGA. I just want to verify the IDCODE and do the boundary scan before configuration. I wired all 8 bank VCCIO (3.3V), VCCPD (3.3V) and VCCINT ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Could you check the nStatus to see if it is high to indicate that the FPGA is ready? May I know what is the issue that you are facing on the JTAG? Do you have another board to test it out?


  • tony_yu's avatar
    tony_yu
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello,

    Thanks for your quick response. Now we are testing the single FPGA chip for our customer, we use jumper wire to connect all the required pins through socket, then power up all power pins (VCCINT, VCCIO, VCCPD) by a power supply instrument and connect all JTAG pins (TCK, TMS, TDI, TDO) to the XJTAG. In the JTAG software, we could not get any return data from TDO. I checked nSTATUS, it was low. Is that means the FPGA is not ready? So how can we let it ready? are there any additional setup?

    Best,