Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
1. Have loaded .sof file via JTAG configuration for batch No is 1713? If the .sof file can be configured via JTAG successfully. Thus it is not a power issue since JTAG configuration is successful. If the JTAG configuration with .sof file failed, thus it is a power issue. Monitor the nStatus signal again. 1. The time when the nSTATUS goes low. Does the nSTATUS signal low from the beginning right after power up? Or during in the middle of configuration process, the nSTATUS from high (logic 1) then suddenly goes low (logic 0)? a. If the nSTATUS is low from the beginning right after power-up, then even JTAG configuration with the .sof file would fail. b. If the nSTATUS from high (logic 1) then suddenly goes low (logic 0) during the middle configuration process, then either due bitstream corruption or power issue. Also, check each power supply voltage level requirement from the datasheet. Troubleshooting Guide:https://www.altera.com/support/support-resources/support-centers/devices/cfg-index/fpga-configuration-troubleshooter.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)