Honored ContributorHi All,
I choose stratix3 for the new design recently.The target is capturing the high-speed signal which is ANSI-644 LVDS. CLK is 600Mhz, data is DDR with 1200Mbps. After reading Stratix3's handbook, I get some doubts. Can I input LVDS @ 600Mhz with no receiver or transmitter to FPGA ? My doubt is receiver or transmitter whether is necessary in LVDS mode?
Honored ContributorYou need to consider using Stratix III's Differential Transmitter & Receivers. Have a look through the high-speed differential i/o interfaces and dpa in stratix iii devices (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/stx3/stx3_siii51009.pdf) section of the Stratix III handbook. This discusses achieving data rates of 1.6Gbps by using dedicated serializer and deserializer blocks.
This is the only way you will get close to the speeds you need with Stratix III. Cheers, AlexHonored ContributorThanks for the reply. It's helpful.
I read this section and find SERDES IP i can use. Another question, my signal has two mode. Mode 1: DDR format, 8bit/frame , every frame 125Mhz, every bit 500Mhz. Mode 2: SDR format, 8bit/frame , every frame 125Mhz, every bit 1000Mhz. How can I set SERDES IP's parameters to work in SDR or DDR mode? best regardsHonored ContributorHonored ContributorYou can use the ALTLVDS to configure your SERDES mode. Since you have 8 bit/ frame, your SERDES factor would be x8. You can then set your data rate to 500M or 1G.
