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Altera_Forum's avatar
Altera_Forum
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10 years ago

Stratix 3 's IO question

Hi All, I choose stratix3 for the new design recently.The target is capturing the high-speed signal which is ANSI-644 LVDS. CLK is 600Mhz, data is DDR with 1200Mbps. After reading Stratix3's ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks for the reply. It's helpful.

I read this section and find SERDES IP i can use.

Another question, my signal has two mode.

Mode 1: DDR format, 8bit/frame , every frame 125Mhz, every bit 500Mhz.

Mode 2: SDR format, 8bit/frame , every frame 125Mhz, every bit 1000Mhz.

How can I set SERDES IP's parameters to work in SDR or DDR mode?

best regards