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macnicaprasad's avatar
macnicaprasad
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10GX

Hi

I am using two Stratix 10 GX L-tile device in my design connecting via through backplane.

chip to backplane and backplane to chip need to send highspeed data rate up to 40Gbps.

My question is need an external phy/retimer in between two FPGA's.

Regards

Prasad

3 Replies

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi Prasad,


    You can use the bit slipper in the L-Tile PHY for word alignment but you need to check manually in soft logic that the correct word alignment is seen.


    As for the retimer, it depends on the losses of the backplane. most customers do not need them but they'll need to simulate to assess the need for a retimer.


    Hope this will help you.


    Thank you

    Kshitij Goel



  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi Prasad,


    As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Thank you

    Kshitij Goel