Stratix 10 PAC HSSI example

I'm trying to understand how to use the hssi interface in stratix 10 PAC. I had some problem on rx_data_valid (PCS Direct on serial loopback)

But unable to reproduce the issue, so i'm creating a new issue to ask how to use it properly.

I tried modifying the hssi_prbs example code, to be more precise i'm trying to change the pattern_gen.v and pattern_ver_pipelined.v into just a simple counter.

However, after changing both of them, the rx_ready is always fluctuating, and never stable at 0xff.

So, i'm at loss on how to actually use this hssi interface. I tried looking into the transceiver user guide but still don't understand how to use it. Can someone please advise me how to use the interface correctly?

here are the modifications to pattern_gen.v and pattern_ver_pipelined.v

// pattern_gen.v

`timescale 1ps/1ps

module pattern_gen #(
        parameter MAX           = 'hffff,       //width
        parameter width         = 16,       //width
        parameter low_freq_len  = 8,        // (width/(low_freq_len*2)) must be a whole number
        parameter pattern       = "prbs7",   // prbs7, prbs9, prbs15, prbs23, prbs31
        parameter prbs_initial_value = 97
    ) (
        input  wire             clk,
        input  wire             reset,
        input  wire             enable,
        output wire [width-1:0] data_out,
        output wire             valid
    );

    reg [width-1:0] counter;
    always @(posedge clk) begin
        if (reset)
            counter <= 'd0;
        else if (enable)
            counter <= (counter == MAX) ? counter : counter + 'd1;
        else
            counter <= counter;
    end
    assign valid    = enable & ~(counter == MAX);
    assign data_out = valid ? counter : 'h0;

endmodule

// pattern_ver_pipelined.v

`timescale 1ps/1ps
module pattern_ver_pipelined #(
        parameter MAX           = 'hffff,       //width
        parameter width         = 16,     // width
        parameter pattern       = "prbs7", // prbs7, prbs9, prbs15, prbs23, prbs31
        parameter prbs_initial_value = 97
    ) (
        input                       clk,
        input                       reset,
        input                       enable,
        input [width-1:0]           data_in,
        output                      data_locked,
        output reg                  error
    );

    reg [width-1:0] ref_value;
    always @(posedge clk) begin
        if (reset)
            ref_value     <= 'd0;
        else if (enable)
            ref_value     <= (ref_value == MAX) ? ref_value : ref_value + 'd1;
        else
            ref_value     <= ref_value;
    end

    reg [width-1:0] err_count;
    always @(posedge clk) begin
        if (reset)
            err_count     <= 'd0;
        else if (enable && (ref_value == data_in))
            err_count     <= err_count + 'd1;
        else
            err_count     <= err_count;
    end

    always @(posedge clk) begin
        if (reset)
            error   <= 'd0;
        else if (data_locked)
            error   <= err_count > 'd0;
        else
            error   <= error;
    end
    assign data_locked = ref_value == MAX;

endmodule