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dncmrc1's avatar
dncmrc1
Icon for Occasional Contributor rankOccasional Contributor
26 days ago

Stratix 10 fPLL pre-calibration

We need to switch (reconfigure) the Stratix 10 fPLL clock rate without waiting for its automatic calibration. For the Arria 10 we disable the automatic calibration and, after power-up, we command a ...
Core Logic
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
19 days ago

The specific register addresses and bit masks for Stratix 10 fPLL calibration results are not publicly documented in the user guides. This represents the differences in the PLL Architecture from Arria 10.

 

The available Register Information that I found in Arria 10 is the fPLL Calibration Enable Registers, where the Offset Address is 0x100.