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Altera_Forum's avatar
Altera_Forum
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17 years ago

strange SCFIFO behaviour

Hi all,

I am experiencing some problems with a "supposed to be" simple SCFIFO. I've instatiated it via the megafunction, but I have 2 problems, one of these driving me a little bit crazy:

1) while running functional simulation, I get this warning: 

Warning: Write to auto-size memory block "selfifo:SelFIFO|scfifo:scfifo_component|scfifo_vh31:auto_generated|a_dpfifo_6o31:dpfifo|dpram_bh11:FIFOram|altsyncram_t7k1:altsyncram2|ram_block3a3" assumed to occur on falling edge of input clock"

but from the documentation it seems that writing to FIFO has to be on the rising edge! Anyway I got this warning also in another DCFIFO implementation, which is working properly, so I'm not too much worried about this (should I?)

2) the biggest problem I have is on FIFO write request: In my code, I have to write to FIFO only when I have a pulse on another signal (accept). I wrote this process to control the FIFO write request: 

FIFO_wr:	process (rst, clk80, accept)	
begin
	if (rst = '1') then fifowrite <= '0';
	elsif ( (accept='1') AND rising_edge(clk80) ) then fifowrite <= '1';
	end if;
end process FIFO_wr;

Seems to be easy, but my fifowrite signal (the write request) keeps staying high even after my pulse (accept) has passed. The accept pulse is not wider than 25 nS.

Any suggestion is really welcome, thanks since now,

C.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    A register holds its value if you don't explicitly change it. So when accept = '1', the signal goes high, but you never turn it back to a 0. So according to your code, it should stay high. I would also recommend keeping the clocking statement in its own. Synthesis may accept it, but it may not work in all tools and is not common practice. Also, most clocked processes have many conditionals within them, so it's usually impossible to join them all together. I would recommend doing something like:

    if (rst = '1') then

    fifowrite <= '0';

    elsif (rising_edge(clk80) )

    if (accept = '1') then

    fifowrite <= '1';

    else

    fifowrite <= '0';

    end if;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi Rysc,

    thanks so much for your answer: I ended using your solution just few minutes before reading your post: I was trying almost everything to make my fifo work, so I tried to "split" the if..then and now it's working (I had the same problem on the fifowrite, now solved). Anyway, I must admit that mine were just tryouts, your solution with an explanation is surely better!

    thanks again, all the best, C.

    PS point 1) of my first post - the warning - is still there.. until it seems to work I don't care of it, but I'm curious why I have this warning!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Not sure on the sim issue. Note that you're writing to the input registers(address, data, etc.) on the rising edge, but there is still an internal memory location that needs to be written to. My guess is this is modeled as a write on the falling clock edge. So outside of the memory everything is positive edge triggered, but the internal model does memory writes on the falling edge.