Honored Contributor
Honored ContributorA register holds its value if you don't explicitly change it. So when accept = '1', the signal goes high, but you never turn it back to a 0. So according to your code, it should stay high. I would also recommend keeping the clocking statement in its own. Synthesis may accept it, but it may not work in all tools and is not common practice. Also, most clocked processes have many conditionals within them, so it's usually impossible to join them all together. I would recommend doing something like:
if (rst = '1') then fifowrite <= '0'; elsif (rising_edge(clk80) ) if (accept = '1') then fifowrite <= '1'; else fifowrite <= '0'; end if;
