Strange problem : Edge capture in a State Machine seems not beeing captured

Is signal "clk_iso2" an actual clock, on a clock net? is it used for clocking logic?

Basically I can see two problems here:

1. If "clk_iso2" is actually a clock, then I would NOT recommend sampleing it at all. Use some other logic instead.

2. Is "clk_iso2" in the same clock domain as "clk"? if it is not, you will need to sample it via two registers to prevent meta-stability. I assume that it isnt in the same clock domain as "clk" as you're having problems, so sampling it is going to throw up all sorts of problems. Also, "clk" must be running faster than "clk_iso2" for you to be able to capture any meaningful changes in it.