Strange PLL Clock causing me failing paths in cyc V design

Dear all,

TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design.

It says failing path with:

Slack______From Node ____________________________________ ____to Node __________Launch Clock ____________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay
-9.115 ____    io_control:io_control_inst1|data_out _______    dq _______    pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk ______  clk_100____    10.000 ____    -10.144______2.901

I wonder what is the problem here and what clock divclk is? The entity io_control flops the data from inside the design and tristating it to dq. dq is an Input / Output Port at the top level design.

IO_control has clock input clk_100. clk_100 is routed globally through the design with an ALTCLKCTRL. The clk_100 is feed to external hardware via ALTDDIO which is consuming dq.

Here is the code of IO_control:

flopping_data_out_proc : process(CLK, RESET)begin
    if (RESET = '0') then
        data_out <= (others => '0');
    elsif (rising_edge(CLK)) then
        data_out <= Fin_DATA_ram;    -- comes from inside FPGA Design
    end if;
end process flopping_data_out_proc;
mux_data_out_proc : process(slrd_en, data_out)
begin
    if (slrd_en = '0') then
        DATA <= data_out;        -- DATA is output of IO Control and wired to DQ
    else
        DATA <= (others => 'Z');
    end if;
end process;

Can somebody enlighten me if this is a critical issue? I set all needed timing constraints but wonder if I had to add a multicycle path or set false path between these clocks?

It is noticeable that the fitter puts out a warning during fitting:

Warning (332049): Ignored create_clock at SDC1.sdc(2): Incorrect assignment for clock.  Source node: CLOCK_50_B5B already has a clock(s) assigned to it.  Use the -add option to assign multiple clocks to this node.  Clock was not created or updated.
    Info (332050): create_clock -name CLK1 -period 20.0 

This is also the clock which feed the pll (clk_100) as reference clock. Can you help me clarifying this issue?

I added the archive file in the attachments.

Thank you for any help.