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Altera_Forum
Honored Contributor
Honored ContributorStrange PLL Clock causing me failing paths in cyc V design
Dear all, TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design. It says failing path with: Slack______From Node ____________________________________ ____to No...
Altera_ForumHonored Contributor
Honored ContributorThe output clock path will still show up as an unconstrained output without the false path. The false path prevents any data path analysis since you're not using this as a data path.
