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If you're getting name mismatch errors, use the Name Finder tool from the GUI dialog boxes you can access in the text editor to create SDC commands (Edit menu). The Name Finder lets you search the timing netlist directly, so the names are guaranteed to be correct.
Not sure why pclk port is not working for you since that should be coming directly from your HDL.
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Ok, with node finder in the TimeQuest gui (used the create_generate_clock button in the Constraints menu) I was finally able to create the correct constraint:
create_generated_clock -name {gclk100} -source .gpll~PLL_OUTPUT_COUNTER|divclk}] -master_clock {pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}
With this the generated clock was correctly created.
With
create_generated_clock -source {get_pins pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} -multiply_by 1 {get_ports pclk} -name gclk100
it is not. Seems to me quartus is rigorous how the constaints should be defined. Especially with the {} ...
One last question and then I will shut up: You mentioned in one of your last posts that I should false path to the output port with
set_false_path -to {get_ports <output port name>}
.
What is the reason for this?
Thank you so much.
Kind regards
Honored Contributor
