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Altera_Forum
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7 years ago

Strange PLL Clock causing me failing paths in cyc V design

Dear all, TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design. It says failing path with: Slack______From Node ____________________________________ ____to No...
Altera_Forum's avatar
Altera_Forum
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7 years ago

If you're getting name mismatch errors, use the Name Finder tool from the GUI dialog boxes you can access in the text editor to create SDC commands (Edit menu). The Name Finder lets you search the timing netlist directly, so the names are guaranteed to be correct.

Not sure why pclk port is not working for you since that should be coming directly from your HDL.