Strange PLL Clock causing me failing paths in cyc V design

You have clk_100 as a virtual clock. If it is actually an output clock, you need create_generated_clock at its output clock port (port is a top-level pin in SDC terminology; pin in the input or output of a cell) with the source as the output pin of the PLL and a false path to that output port as well so the path doesn't get analyzed as a data path.

You also need set_input_delay constraints and matching -min set_output_delay constraints.

As for the warning about dual clocks on one of the inputs, you'll have to look at/post the clocks report to see what's going on there.