Honored Contributor
Honored ContributorHi Rysc!
My Shift Register is toggling at 25MHz. (The Master clock on my board is 50MHz). It is now implemented in RAM again. I only tried to implement it into logic-elements, after endian wrote something about it. If I do so, my whole FPGA is nearly a single shift register. That does not work for me, because I need some logic besides the shift register. So finally, I advised the synthesis tool to put it into RAM again. The signals I shift through it are 11 bit wide data. And the depth of the shift register is now 630. So one can say it is a 630x11 bit shift register. Before, it was a 850x11 bit shift register. In the future I will need again the bigger one, but for now, it works as it is. About the data, one has to know that it is not every bit of the shift register 'filled' with a high value at a time. Normally, I have 4-5 11 bit words filled with data. In between them, the shift register elements are all empty. I would have never thought, that it does consume that much power. . . Besides the FPGA, my board has to drive the UART IC+line and an ADC evaluation kit at 25MHz. Maybe alltogether is to much for the power supply, although I am a little bit disappointed about the fact, that it can't handle that . . . Greets and thanks for your support! Maik
