Honored Contributor
Honored Contributor@Rysk: Thank you for your extended answer. Honestly, I didn't expected something like that on my vague question.
I set all my unused pins to "As input tri-stated". Otherwise, I had some more strange effects with a lot of pins toggeling, which lead to periodic re-configuring of the device. Unfortunatly for my problem, this means, that you don't have a clue, either, about this D19 problem . . . In my Control Signals tab, I have only one 'Clock'. The other stuff is all 'Clock enable' and 'Sync. clear' which, I guess, is logic implemented by the synthesis. Signal Tap is completly new to me. However, if you recommend to use it, I have to take a look at it, to figure out what it even does. @endian: Thank you for your answer, too. In fact, I always thought, that the RAM-block based implementation of my shift register is the better way. Moreover, I noticed an opposite effect. I extended my shift register for a test with 10 more shift lines, and after that it was implemented in logic-elements. After reducing the shift register size, it was in RAM, again. The advantage of the RAM implementation is, that simulation is a lot faster, than with the logic elements. . . Anyway, what in your eyes is the advantage of a shift-register in logic-elements than in RAM-blocks? (I just tried to implement the shift-register in legic-elements. Now, I have a total logic-elemts usage of 10551/10570 (100%). That means I don't have much left to implement some additional logic . . . :rolleyes: ) Greets Maik
