Strange effect with Stratix FPGA

Are all the pins assigned? That's one possibility, that something that is not assigned gets put onto D19(although not that likely to repeat). If you go to Assignments -> Device -> Device and Pin Options -> Unused Pins(tab), what is this set to? Basically this controls the pins you haven't assigned, including D19. If it's set to Outputs Driving an Unspecified Signal, then it's possible that it is toggling. There was an earlier thread with a list of things to look at when starting a project, and I believe this was on there.

As for the rest of it not matching the simulation, how many clocks do you have in your design? A useful thing I do is open the report file, go to Fitter -> Resource Section -> Control Signals and sort on Usage. This will list all the clocks in your design together. Note that this is slightly different to timing analysis clocks, as it shows every node that drives the .clk port of a register. So gated clocks will show up here, while during timing analysis the gated clocks are usually just part of the domain that drives them.

If everything is synchronous and passes timing, then you may need to pull out SignalTap. I believe almost every FPGA design should plan on using SignalTap, as once you get the hang of it, it's a blessing for debugging your logic. (I say this as you need to plan to use some logic and a decent amount of memory resources to do SignalTap).