Still cannot assign LVDS signal to MAX-V device

Can you archive your project and post it here.. let us check it out.. Maybe you can also download the latest 18.1 version and try in the meantime.

Attached is the archive file. I have to change the file extension to text otherwise I can't upload it. (the Answer button gets gray out when it is of type ".RPT")

I have already tried Quartus 18.1 with no luck.

I choose LVDS_E_3R because MaxV only support this.

The file was able to compile when I change only this pin to another I/O standard but fail when I change it back

This is the archive report file and is useless for me. Please upload the .QAR file. I can then check what the issue is about. You can upload the QAR file in this forum and I've done it earlier.

see attached, Is this the right file you need

I've looked into the project and resolved the LVDS issue. I've deleted the ALTLVDS_TX IP as it is not needed, but haven't removed the other IP components. If you are not using these, please do remove them.

Another point to be noted is that I've used v18.0 lite and created this QAR file, so I would suggest you open this file with v18.1 and upgrade the IP components. Then do a PRoject Clean and then Compile. It should work this time. The LVDS assignments are OUT_P(p) -> PIN_D15 and OUT_P(n) gets assigned to PIN_C14. It compiles fine without the errors.

But I never use the ALTLVDS_TX IP in my design. I only have it there because my LVDS signal was causing compile issue and was trying out this part, it didn't help and I have commented them out as seen at the bottom of my file. I try this design in using V18.1 lite and it didn't work.

Attached is the 18.1 archive.

I un-archive your design and it compile but What did you do to the designed to get it to work

The only different I noticed is that my pin planner assigned OUT_P(N) to C14 and yours is empty.

I try duplicating it by deleting OUT_P(N) but this also remove OUT_P(P), therefore I can't seem to it.

SInce Mine still didn't work with v18.1 lite, ........What did you do to get it to work

I try to edit the archive with the pin planner that you returned to match the pinout with my design for OUT_P(N) to C14 at the column "Location" but Quartus said "Editing location assignment is not successful. The differential pair pin is assigned" I won't allow me to edit this field. even thought the column "Filter Location" said PIN C14.

I thought these two column (Location and Fitter Location) are the same.

Your Archive has this field (Location) empty but mine have this field set to C14.

I'm confused,.

attach is the different between mine and yours.

I fact when I try to put c14 into your archive, the tool crash

OK, I have recreated the problem that I have but I 'm still dont know how to fit it.

I took the archive that you send to me. It compile OK.

Now I change the the signal "OUT_P" to cmos and IOBank to 3.3v and that compile

Next I change it back to lvds and IOBank to 2.5v, now pin planner creates the other diff signal and assigned C14 to it.

Now it crash just like before.

I cannot get it back to the state that you sand me where the Location field for OUT_P(N) is empty.

It is when this field is empty then it compile.

How did you get this field to be empty