Forum Discussion
Still cannot assign LVDS signal to MAX-V device
I try your suggestion. I have a single-ended signal call OUT_P and assigned it as LVDS_E_3R, the pin planner created the corresponding diff signal call OUT_P(P).
When I compile it, Quartus returns a pop-up problem report window.
The short version of the Preview of the report :
Problem Details
Error:
Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op_place.cpp, Line: 1882gid != DEV_ILLEGAL_GLOBAL_IDFitter pre-processing
Stack Trace: ....................................
................................
Executable: quartus_fit
Comment:
None
System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0
Quartus Prime Information
Address bits: 64
Version: 17.1.0
Build: 590
Edition: Lite Edition
14 Replies
- Abe
Frequent Contributor
Hi,
Sorry, it was past my bedtime earlier. Well, here's what I did to resolve the issue:
- Remove the ALTLVDS IP.
- Clean the Project
- Remove the C14 OUT_P(n) assignment since the tool will assign this automatically. (Assignment Editor)
- Made sure the IO Standards are correct. Bank 2 in your project is configured for 2.5V, the OUT_P signals cannot be assigned to 3.3V LVCMOS/LVTTL standards. This should be 2.5V only.
- Assign only the OUT_P signal to PIN_D15 and compile the design. The Tool automatically assigns PIN_C14 for the OUT_P(n) signal (Emulated LVDS pair) and compiles the design.
- Used Pin Planner tool and not Assignment editor to make the assignments.
Point to be noted -
When assigning / working with LVDS , the core logic will always be single-ended. We assign only the +ve PIN of the device to the output signal and set the IO Standard as LVDS and match the IO Voltage to the one the Bank is using.
The -ve (pair) signal need not be assigned manually in the Pin Planner or Assignment editor. Assigning this will cause the tool to generate errors and the compilation to fail. This is coz the tool generates and assigns the LVDS pair automatically.
Hope this clears your doubts. You need not generate the +ve and -ve LVDS signals in your VHDL code. Just use the single-ended logic like always. Assign the LVDS output signal to the (p) Pin in Pin Planner/Assignment editor, set IO standard to LVDS and compile. The tool will do the rest.
I've modified the v18.1 project file you sent and tested it. It compiles fine. You can check it out.
- TChin5
New Contributor
Hi,
According to your reply in step 6, I did use pin planner to assign my lvds. Once I assigned "OUT_P" with IOStandard=LVDS and Location=D15.
Pin Planner automatically assigned C14 to OUT_P(N).
I didn't touch this other diff signal, Pin planner assign it. If you look at my design with Pin planner, yours has an empty location field there but mine has it populated with C14. see attachment
This cause my compilation to fail and your to pass
I did try to compile the design you send back and it pass but I cannot duplicate it on mine side.
I cannot get that empty location field to show up.
Even after I delete it and reassigned it to the positive-end, pin planner always assign the negative-end and fill that location field
- cossy
New Contributor
Hi TChin5:
I have tried the proj, in the end i find one thing:
when you assign the LVDS pin, the .qsf maybe like below:
"
line 1: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to send_dataline 2: set_location_assignment PIN_78 -to send_data
line 3: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to "send_data(n)"
line 4: set_location_assignment PIN_77 -to "send_data(n)"
line 5: set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp"
you should del the line 3 and line 4 manually , and compile it , then you will see the send_data(n) pin assignment is null, and it can be done.
I haven`t test the real LVDS signal recently . will try later
BR
Seiya
- cossy
New Contributor
Hi TChin5:
I have tried the proj, in the end i find one thing:
when you assign the LVDS pin, the .qsf maybe like below:
"
line 1: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to send_dataline 2: set_location_assignment PIN_78 -to send_data
line 3: set_instance_assignment -name IO_STANDARD LVDS_E_3R -to "send_data(n)"
line 4: set_location_assignment PIN_77 -to "send_data(n)"
line 5: set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp"
you should del the line 3 and line 4 manually , and compile it , then you will see the send_data(n) pin assignment is null, and it can be done.
I haven`t test the real LVDS signal recently . will try later
BR