Still cannot assign LVDS signal to MAX-V device

Hi,

Sorry, it was past my bedtime earlier. Well, here's what I did to resolve the issue:

1. Remove the ALTLVDS IP.
2. Clean the Project
3. Remove the C14 OUT_P(n) assignment since the tool will assign this automatically. (Assignment Editor)
4. Made sure the IO Standards are correct. Bank 2 in your project is configured for 2.5V, the OUT_P signals cannot be assigned to 3.3V LVCMOS/LVTTL standards. This should be 2.5V only.
5. Assign only the OUT_P signal to PIN_D15 and compile the design. The Tool automatically assigns PIN_C14 for the OUT_P(n) signal (Emulated LVDS pair) and compiles the design.
6. Used Pin Planner tool and not Assignment editor to make the assignments.

Point to be noted -

When assigning / working with LVDS , the core logic will always be single-ended. We assign only the +ve PIN of the device to the output signal and set the IO Standard as LVDS and match the IO Voltage to the one the Bank is using.

The -ve (pair) signal need not be assigned manually in the Pin Planner or Assignment editor. Assigning this will cause the tool to generate errors and the compilation to fail. This is coz the tool generates and assigns the LVDS pair automatically.

Hope this clears your doubts. You need not generate the +ve and -ve LVDS signals in your VHDL code. Just use the single-ended logic like always. Assign the LVDS output signal to the (p) Pin in Pin Planner/Assignment editor, set IO standard to LVDS and compile. The tool will do the rest.

I've modified the v18.1 project file you sent and tested it. It compiles fine. You can check it out.