Forum Discussion
Honored ContributorState A => State B multicycle path?
Is there a way to tell TimeQuest that all signals launched by State A and captured by State B are part of a multi-cycle path? My combinational path delay is too large so i'm adding a timer to delay my FSM state transition by one extra cycle. Previously, I have been using the SDC per below but I wonder if there is a way to tell TimeQuest that any signals travelling between the launch and latch FF's are multicycle?
set_multicycle_path -setup -end -from [get_keepers {main_controller:main_controller_inst|reg_rx_regs_offset[*]}] -to [get_keepers {tx_tlp_buffer:tx_tlp_buffer_inst|mem[*][*]}] 2 set_multicycle_path -hold -end -from [get_keepers {main_controller:main_controller_inst|reg_rx_regs_offset[*]}] -to [get_keepers {tx_tlp_buffer:tx_tlp_buffer_inst|mem[*][*]}] 2 Thanks23 Replies
Altera_Forum--- Quote Start --- In my case, the target register is *using* the signal after two cycles. Therefore, the signal is being clocked on every tick but I only care about the signal state every other state (when my timer expires). In essence, it is a form of clock enable but in the form of a delayed FSM transition. --- Quote End --- As I mentioned, the multicycle applies only in two cases: the register is not allowed to clock in at every edge through enable or the it is allowed but the D data is not allowed to transition at after every clock edge. If the latch register cares about data every other clock but data may change every clock then you cannot apply multicycle because the register will be affected by violations. So you are in best position to see which of your registers can be multicycled. If state registers transition every other clock then you can apply multicycle to state registers (rather than signals in between)- Altera_Forum
In my case, the target register is *using* the signal after two cycles. Therefore, the signal is being clocked on every tick but I only care about the signal state every other state (when my timer expires). In essence, it is not a clock enable but rather a delayed FSM transition.
I suppose the SDC 'set_multicycle_path' must be specified on each and every signal part of the multicycle path like above. I essentially wondered whether it would be possible to state something like: set_multicycle_path -setup -end -from [Launch_FF] -to [Latch_FF] 2 Theorethically, then, the timing analyzer would know which signals are launched by Launch_FF and clocked in by Latch_FF and therefore know that all signals launched by Launch_FF would have 2T to reach the Latch_FF. But perhaps, it simply is not possible and I will have to specify each signal separately? I'm currently doing this (spec'd separately) and it is working fine. Thanks. - Altera_Forum
A multicycle applies when a register is clocked not at every edge but every other edge or so. In your case I assume by timer you mean clock_enable. If so you can apply multicycle to all registers activated by clock_enable.
Edit: Similarly a multicycle applies if data is known to change every other clock or so. However just having data delay is not a case for multicycle approach.
