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In my case, the target register is *using* the signal after two cycles. Therefore, the signal is being clocked on every tick but I only care about the signal state every other state (when my timer expires). In essence, it is a form of clock enable but in the form of a delayed FSM transition.
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As I mentioned, the multicycle applies only in two cases: the register is not allowed to clock in at every edge through enable or the it is allowed but the D data is not allowed to transition at after every clock edge.
If the latch register cares about data every other clock but data may change every clock then you cannot apply multicycle because the register will be affected by violations.
So you are in best position to see which of your registers can be multicycled. If state registers transition every other clock then you can apply multicycle to state registers (rather than signals in between)
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