Forum Discussion
Altera_Forum
Honored Contributor
13 years agoIn my case, the target register is *using* the signal after two cycles. Therefore, the signal is being clocked on every tick but I only care about the signal state every other state (when my timer expires). In essence, it is not a clock enable but rather a delayed FSM transition.
I suppose the SDC 'set_multicycle_path' must be specified on each and every signal part of the multicycle path like above. I essentially wondered whether it would be possible to state something like: set_multicycle_path -setup -end -from [Launch_FF] -to [Latch_FF] 2 Theorethically, then, the timing analyzer would know which signals are launched by Launch_FF and clocked in by Latch_FF and therefore know that all signals launched by Launch_FF would have 2T to reach the Latch_FF. But perhaps, it simply is not possible and I will have to specify each signal separately? I'm currently doing this (spec'd separately) and it is working fine. Thanks.