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Altera_Forum
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13 years ago

State A => State B multicycle path?

Is there a way to tell TimeQuest that all signals launched by State A and captured by State B are part of a multi-cycle path? My combinational path delay is too large so i'm adding a timer to delay m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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So, after T2 clock edge, Latch_FF will (most likely) have a correct value.

But what Downstream_FF will be latching at the T2 clock edge is based on what Latch_FF had prior to the clock edge -- a bad value.

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But if the output of Latch_FF isn't considered to be 'valid' until T2 then

the Downstream_FF won't be 'using' this value until T3 at which point it

will be a solid '1' or '0'.

?

I think I'd rather find a work around to this but think that what the OP says is true (with the caveat about registering the correct output at T2).

Nial.