Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- If a FF hasn't resolved to a stable state by the next clock edge, it's normal timing characteristics (tSU, tH, tCO) may not apply. Hence, it's not 100% sure that it will behave normally. --- Quote End --- Once again, I agree. The metastability may settle out on the next clock edge, but in the mean time, it may cause other registers down stream to go metastable. In addition to that, it also creates noise in a circuit which can cause crosstalk to other nearby traces. As I said before, set your multicycle hold to 0, then if you meet timing it won't go metastable. If you can't meet the hold time, then add a clock enable.