SRAM 160MHz, impedance matching

FVM said "Setting the FPGA outputs to minimum current strength gives a suitable impedance for many applications. A series termination can't be assigned for 3.3V LVTTL as far as I know".

What is minimum current strenght, and how to use it?

set_instance_assignment -name current_strength_new "minimum current" -to data_bus[0]????????????????????

thank you

not pretty sure if this info helps

in cyclone2 device if you feel clock output is not stable, maybe you have to review the power supply of pll. i have a friend who struggle this for a long time just Vco for pll issue. this does not seem in cyclone 1 & 3.

Current strength can be comfortably set in the Quartus Pin Planner. You have to add a "current strength" column in the pin list by the "Customize Columns" function in the context menu.

Generally, it's recommended to check the actual signal waveforms at the load with a low capacitance probe.

Hello,

I changed the pin assignement to "minimum current strenght" but in the output there are more noise.

Why I can not use the termination 50 Ohms series resistance?, when I try to use it I have this error:

Error: I/O standard 3.3-V LVTTL on output I/O pin D0_bus_B cannot have Termination logic option setting Series 50 Ohm.

I still have problems with the Impedance matching, and I can not check the actual signal waveforms at the load with a low capacitance probe. In my board there is no way to connect an osciloscope.

Bye and thanks.

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but in the output there are more noise

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How can you determine this without watching the waveforms?

You also didn't tell about the observed problems. Apart from Cyclone III I/O constraints, there can be no real impedance matching with the involved standards. You can at best achieve a source sided series termination of the address and control signals, but it's threatened by the SRAM input capacitance. Any achievable termination will be a compromise. With the data lines, you would need source sided termination for both directions. I guess, you also don't know about the exact trace impedance in your design, and most likely coupling between signals is an issue. In this case, how to check for correct operation without a measurement? I don't know.

My normal procedure would be to check the waveform and try different current strength settings. I can hardly imagine, that you don't have at least a few signals that can be probed. Altera has set a limitation to selectable I/O settings at high VCCIO (3.3 and 3V, if I remember right). Before taking 50 ohm termination into your head, you should check the behaviour with the available settings. Small PCB traces have rather 70 than 50 ohm impedance. If the observed waveforms actually indicate too high impedance, you should report.

How can you determine this without watching the waveforms?

R/

After test and simulate almost all the design, I suspected it was something with the impedances.

So, I played a little bit with the assignation of the pins, and the resultats of the output change.

For example if I change the assignation of the LSB and the MSB bit of the DATA BUS of the SRAM, in the output I can see drastical changes.

DABG

Hello,

Maybe I am not clear with my explication.

Please look the attached image.

Is the test that I did.

Can I conclude that my bug is related with the Impedance matching, I have not way to look the signal with an osciloscope.

Thank you.