Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

SR flipflop problem

Hi. I made a SR ff code, and compile is done well.

but when i simulated this code.... It looks different from what i made.

(p.s please don't say that use the D flipflip!! I just want to know what the problem is

in my code!! Thanks!)

this is code

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY flip is

PORT(

s, r : in std_logic;

q, nq : inout std_logic);

end flip;

ARCHITECTURE arc of flip is

begin

process(q,s,r)

begin

if(s='1' and r ='1') then

q<='1';

nq<='1';

else

nq<= s xor q;

q<= r xor nq;

end if;

end process;

end arc;

and this is simulation image!!

http://image.kilho.net/?pk=1013878&from=web

(p.s is there anyone who know how to insert the image in here?)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    1. why are q and nq inouts? they just want to be out

    2. you're missing nq from the sensitivity list.

    3. this is not a flip-flop, there is no clock.

    4. shouldnt reset have preference over set?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I think you are talking about the basic SR FF. This was done by connecting two nor gates in feedback (or two nand gates). So all you need is a combinatorial circuit:

    q <= r nor qn;

    qn <= s nor q;

    s & r should be either 00,01,10 but not 11 hence the further development to D where S &R inputs were replaced by one input D that acts as S and internally inverted to act as R.

    You may need to insert delays if your output vibrates.