Hi, everyone I am using SPI Master Core on FPGA to transmit data to SPI slave (offboard device). I want to use DMA to free my NIOS for other tasks during SPI data transfer. My Idea is NIOS - DMA - SPI(master) <-> SPI (slave / extern device) I can not understand, how can it work. SPI master core send and receive data at the same time. After sending, e.g, 8 bits data I also have to read the 8 bits data in RXdata register which resets RRDY bit in status register. Otherwise I will get a ROE (Receive overrun error), If I send another 8 bits data. If I use DMA to send, e.g., 20 bytes data continiously without reading any data from SPI Rxdata, I will definetely get error and Sending will not be successful. Has someboby really used SPI with DMA to send data? How can it work? Thanks a lot!

Why not to use SPI to Avalon-ST and SGDMA? SGDMA would transfer the data, when SPI core is ready.

Thanks U a lot dear Socrates Do U have an Example ? QSys & Source Code. If I use SGDMA, I will need a SGDMA memory to steam for TX. Do I also need a SGDMA stream to memory for RX to avoid RX overrun error? I do not need to receive data.

I've not used SPI with Avalon-ST interface, but since it's a streaming interface, there should be no problems if You will not use data reception part, since it's not keeping data in any buffer. Check documentation.

Thanks again Socrates! I don't think it is a problem with DMA or SGDMA, but with SPI. I must receive RXdata everytime I have sent TXdata. Or I would get Receiver Overrun Error. I don't want to interrupt Txdata channel after each sending in order to receive unused Rxdata and so to reset RRDY bit in status register. has somebody Idea?

SPI with Avalon-ST is a different component than simple SPI, which has Avalon-MM interface, so there are no interrupts, no overrun errors and that kind of stuff! Either You don't understand what I am talking about or this task is too difficult for You.

SPI with DMA is not working? | Altera Community

20 Replies

Altera_Forum
Honored Contributor
13 years ago
Would have been nice(r) if you gave the actual MPU part-number.

SPI interfaces differ from device to device, so I wrote a general SPI-master interface handling some of the differences. I recently wrapped this in a MM-Slave block.

I have no idea if modifying the Altera supplied SPI module is straightforward. (They are in Verilog, and I do VHDL ...). A lot of the Qsys building blocks are NIOS II oriented and thus driven by software. This complicates things now and then.
Altera_Forum
Honored Contributor
13 years ago
It is interfaces on LCD controller which is called SSD1325.

---------------------------------------
MPU Interface selection

SSD1325 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface mode is summarized in Table 6. Different MCU mode can be set by hardware selection on
BS[2:0] pins (please refer to Table 5 for BS[2:0] setting).

Table 6 : MCU interface assignment under different bus interface mode

Pin Name D7 D6 D5 D4 D3 D2 D1 D0 E R/W# CS# D/C# RES#

parallel interface
8-bit 8080 D[7:0] RD# WR# CS# D/C# RES#
8-bit 6800 D[7:0] E R/W# CS# D/C# RES#

or
SPI SDIN SCLK Tie LOW CS# D/C# RES#
Altera_Forum
Honored Contributor
13 years ago
The receiving device is clear to me now.
I (re-)checked the documentation on the SPI-core in the Embedded Peripherals Guide, and it is effectively meant to be driven by software. The module has no waitrequest signal to hold of successive writes (read) until each SPI transfer has finished.
Altera_Forum
Honored Contributor
13 years ago
I found another issue.

just for testing I shut off RX path and use DMA to stream 5 bytes data to SPI TX holding register. but no success!
I could only send 2 bytes and then I got a TOE.
SPI has signal "readyfordata" als flow controll. But I can not find any signal somehow like that on DMA write master, which leads DMA send the 5 data to SPI without considering if SPI is ready or not.
How does DMA controll data flows?

Thanks
Altera_Forum
Honored Contributor
13 years ago
Avalon MM master : waitrequest
Avalon MM slave: dataavailable, endofpacket & readyfordata

How can it work? Thanks
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Avalon MM master : waitrequest
Avalon MM slave: dataavailable, endofpacket & readyfordata

How can it work? Thanks
--- Quote End ---

It doesn't. The MM interface hasn't got a waitrequest to hold the DMA off, effectively resulting in a TXOverrun at the second write.
The dataavailable and readyfordata are internally connected only and read as 'status' signals by a Nios II CPU.
Maybe you can try inverting the readyfordata and use that as a waitrequest.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
It doesn't. The MM interface hasn't got a waitrequest to hold the DMA off, effectively resulting in a TXOverrun at the second write.
The dataavailable and readyfordata are internally connected only and read as 'status' signals by a Nios II CPU.
Maybe you can try inverting the readyfordata and use that as a waitrequest.
--- Quote End ---

In V file I found

// Ready to accept streaming data.
assign readyfordata = TRDY;

the signal readyfordata indicates if Transmit ready bit is set. Inverting the readyfordata/TRDY for every write prevents my NIOS from doing other tasks. Or do U mean I should change hardware to do it? thanks
Altera_Forum
Honored Contributor
13 years ago
Of course you would have to modify the logic source and create a new module.
If you want to access that module both from the Nios II CPU and from a DMA controller, things get complicated. That complexity is now handled by the Qsys fabric that 'separates' the two masters accessing the same slave. If you hack the SPI source into an output-only SPI with waitrequest you should be able to connect both the CPU and the DMA controller, but you will have to re-write the software driver as well.
Altera_Forum
Honored Contributor
13 years ago
I am still wondering cause I found the following sentence in document ug_embedded_ip. So I have to understand there is a bug in document?
actually UART has the same interface as SPI for data transfer. So can I neither use DMA to stream data to UART?

"The SPI core can be used in conjunction with
a DMA controller with flow control to automate continuous data transfers between, for example, the SPI core and memory."
Altera_Forum
Honored Contributor
13 years ago
I actually build a minimal system in Qsys and generated the system to inspect the code. I exported both the MM Slave interface and the SPI conduit.
I played around with the checkboxes etc. but the HDL example didn't change ... no waitrequetst signal showed up.
So I think it doesn't work without some extra work.

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SPI with DMA is not working?

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