Open Side Menu
Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. FPGA Device

Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

SPI Slave to Avalon Master Bridge Design Example - no qsys file in zip?

Hi,

I want to modify the SPI Slave to Avalon Master Bridge Design Example for a DE1-soc board, which is located here:

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html

(https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html)

There is no .qsys file in the .zip?

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    I think there is Qsys file in here - https://cloud.altera.com/devstore/platform/16.0.0/spi-slave-to-avalon-master-bridge-for-cvsx/

Recent Discussions

  • BrianSune_Froum's avatar
    Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
    13 hours ago
    BrianSune_Froum
  • Robert_PIN_ASAP's avatar
    Agilex 3 VCCLSENSE and GNDSENSE
    17 hours ago
    Robert_PIN_ASAP
  • przemyslaw_pajak's avatar
    Mac internal loopback F-Tile, Quartus 25.2
    1 day ago
    przemyslaw_pajak
  • FabriceNs's avatar
    Request for ESD and Reflow Information
    1 day ago
    FabriceNs
  • Jonas's avatar
    How to Simulate the ADC IP from MAX 10
    1 day ago
    Jonas
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo