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Altera_Forum
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16 years ago

SPI Pin Assignments

Hi,

I ran into a problem trying to assign the MOSI_out_from_SPI signal and/or the SCLK_out_from_SPI signal. I looked in the Altera documentation and it does not appear that these signals require anything special (as far as type of pin to use), so I am certainly confused.

I had been using some digital pots in my design, and I used two bits from a 16 bit PIO to bit bang the data into the devices. In my latest revision, I used SPI interface digital pots. I had planned to just reassign the spi interface pins to the same pin locations as I used for the individual bits from the PIO, since the layout for these two lines (MOSI AND SCLK) on the PCB did not change.

I can remove the connections for the old PIO bits to the FPGA pins, recompile, and the systems accepts the program from the debugger. I can remove the ‘OLD’ assignments for the MOSI_out_from_SPI pin and the SCLK_out_from_SPI pin, leave them blank, recompile, and the systems accepts the program from the debugger.

If I try to assign EITHER of these two pins (MOSI or SCLK), the system compiles fine, but when I try to it will not download to the system (via NIOS II Debugger) I receive the following error from the debugger;

using cable "usb-blaster [usb-0]", device 1, instance 0x00

pausing target processor: not responding.

resetting and trying again: failed

leaving target processor paused

Any ideas on why this is occurring? Thanks.

Fred

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm pretty confused. So if I understand correctly you've got two pins on the FPGA that you are using for an SPI interface to some digital POTS. In general, this should have absolutely nothing to do with the error you are getting. The most common cause for the error you are getting is either a stuck reset signal or no clock to the NIOS processor.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I too am confused. I compiled the system about 5 or 6 times today to try different combinations; if I leave the two pins with their old assignments, everything works fine, if I reassign the two (only using MOSI and SCLK) to the previous location I was using for the individual pio lines (i.e. 2 bits), the debugger would not download and threw the message I indicated earlier. If I leave the two PIO lines blank in the pin definition, it works...

    I am beginning to think it may be some sort of incompatibility/bug within the Cyclone II or the SPI core. If I reposition the location of the SPI within the SOPC builder, would this change the location within the FPGA? I am just trying to think of some work around to resolve this impasse. Any ideas are welcome!! Thanks.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    jakobjones,

    I started thinking about your email last night, and when I got in this morning I looked at the project again, specifically at the 'reset'. Somehow, my PLL 'locked' signal was not named properly, and I think the FPGA was able to run in one configuration but hung in another because the reset line was not being conditioned properly. After fixing this, the system compiles and downloads/runs fine. Thanks for pointing me in this direction. Have a great weekend and take care.

    Fred