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Altera_Forum's avatar
Altera_Forum
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10 years ago

SPI Core without AXI/Avalon interface

Hi All,

I need a SPI Core, which is able to receive a hardware trigger in order to start its transmission.

It should not be connected neither to Avalon nor AXI3 buses. All the configurations (clock polarity, etc) should be done/configured during the core creation.

Does Altera has such core? The only SPI Core, which I found in the IP-Catalog, is the Avalon-ST Serial Peripheral Interface (SPI). This Core does require the Avalon/AXI3 connection.

So, do you have a Core, which might be instantiated in the FPGA portion of ArriaV and which does not require a connection to HPS?

Thank you!

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    hi, how sure what is your purpose if usage, with out Avalon means the only option is to utilize the hps spi core??

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    No, I actually need SPI, which could work without any software intervention. Actually I need to shift data in, there is no need to shift any data out. So, the only hardware trigger should be used in order to start a transaction. The shifted in data should be read by hardware only, also without any software integration.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I know there are only 4 lines in the SPI protocol...

    My question was whether Altera has a ready-for-use SPI core, which is able to work without any software intervention...
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The SPI core you've already found is the only SPI IP Altera offer. I'm sure there are third party offerings. However, they're likely to connect to Avalon bus too.

    You can always export the Avalon interface and control the SPI core from your own rtl, thus avoiding any 'software intervention'. Is that you're goal? You're not very clear on how you wish to control the SPI core other than not from software...

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    You can always export the Avalon interface and control the SPI core from your own RTL, thus avoiding any 'software intervention'

    --- Quote End ---

    Hm... Should I implement an Avalon interface in RTL, which "write" to SPI core in order to initialize the SPI transaction?

    Actually the SPI should be connected to an external device and should read a data from it every 10msec... So, my original purpose was to create some timer/counter, which gives a trigger to SPI every 10msec... Now I understand I need to create some RTL block, which not only gives such trigger, but also implement an Avalon interface and "write" to one of the SPI registers in order to start a transaction... Is that true?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, that's basically right.

    Read through the spi core (https://www.altera.com/zh_cn/pdfs/literature/hb/nios2/n2cpu_nii51011.pdf) chapter of the Quartus II Handbook. Export the 'spi_control_port' interface in Qsys to present the Avalon Memory-Mapped (Avalon-MM) control interface. This gives you access to a simple, memory mapped address space from which you can control the SPI core. You can write some simple rtl to control this.

    Refer to table 7-3 on page 7-10 for the Register Map. I hope that looks reassuringly straightforward. Descriptions of each register follow. A write to the 'txdata' register will generate the SPI transaction you're after. Then wait 10ms and write to it again. Recover any data read back from your device via the 'rxdata' register.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Yes, that's basically right.

    Read through the spi core (https://www.altera.com/zh_cn/pdfs/literature/hb/nios2/n2cpu_nii51011.pdf) chapter of the Quartus II Handbook. Export the 'spi_control_port' interface in Qsys to present the Avalon Memory-Mapped (Avalon-MM) control interface. This gives you access to a simple, memory mapped address space from which you can control the SPI core. You can write some simple rtl to control this.

    Refer to table 7-3 on page 7-10 for the Register Map. I hope that looks reassuringly straightforward. Descriptions of each register follow. A write to the 'txdata' register will generate the SPI transaction you're after. Then wait 10ms and write to it again. Recover any data read back from your device via the 'rxdata' register.

    Cheers,

    Alex

    --- Quote End ---

    good input, this providing user more option to control the spi.