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Altera_Forum
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10 years ago

SPI Core without AXI/Avalon interface

Hi All, I need a SPI Core, which is able to receive a hardware trigger in order to start its transmission. It should not be connected neither to Avalon nor AXI3 buses. All the configurat...
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Altera_Forum
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10 years ago

Yes, that's basically right.

Read through the spi core (https://www.altera.com/zh_cn/pdfs/literature/hb/nios2/n2cpu_nii51011.pdf) chapter of the Quartus II Handbook. Export the 'spi_control_port' interface in Qsys to present the Avalon Memory-Mapped (Avalon-MM) control interface. This gives you access to a simple, memory mapped address space from which you can control the SPI core. You can write some simple rtl to control this.

Refer to table 7-3 on page 7-10 for the Register Map. I hope that looks reassuringly straightforward. Descriptions of each register follow. A write to the 'txdata' register will generate the SPI transaction you're after. Then wait 10ms and write to it again. Recover any data read back from your device via the 'rxdata' register.

Cheers,

Alex