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ThomasKendall82's avatar
ThomasKendall82
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5 years ago
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Specify init file to inferred BRAM

Hello

I've been trying to write an inferred memory with init file, but i can't manage to cause Quartus to initilize it.

First, I tried to use TEXTIO to configure initial value. I've read that Quartus doesn't support it, so I tried using MIF files as alternative.

I wrote a MIF file and linked it using the RAM_INIT_FILE attribute, but it seems like quartus ignored it.

When I ran PnR I did noticed that quartus mentioned MIF files only when creating ones itself - the new ones were all zeros and these were implemented instead of my MIF files.

I'm aware of the option to generate initilized ram in quartus, but I'm trying to make the inferred memory work with init file - So Im looking for a way to take care of the init file in the VHDL file only, without additional work in quartus.

The code I've wrote is in VHDL 2002 and was tested in quatus 14. (I don't have an example at the moment, but I can add if its required).

I wrote the MIF solution according to the following instructions :

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/reference/glossary/def_mif.htm

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_ram_init.htm

Thank you in advance.

  • ThomasKendall82's avatar
    ThomasKendall82
    5 years ago

    Hello,

    I'm sorry for the late response - I've been busy for the last few days.

    I tried to create a simplified example of the problem (as some of you requested) -I re-wrote it based on quartus code templates and the mif file was used correctly.

    After further inspection - I've noticed that my TextIO based initialization function, which should have been for simulation purpose only, did reset the memory to zero even when the TextIO part was not working.

    I overlooked that part untill now because it was supposed to be for simulation only and I was sure it didn't had any effect.

    I think that attribute didn't work because the function already declaired an initial value. (quartus did create a mif file for the zeros the function set to the memory)

    After I've changed that part in the function the attribute worked and all was well.

    Thank you all for your help and advice.

8 Replies

    • ThomasKendall82's avatar
      ThomasKendall82
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hello,

      As of your proposal- I tried to upgrade the Quartus version and see if the problem presists.

      I've checked the same code on Quartus 18.1 (Had it pre-installed) and it seemed the same.

      Generally - I'm looking for a solution that will be supported on older versions such as 14.1, so I cannot accept a Quartus upgrade as a valid solution - but if checking it on 20.1 might help to analyze the problem I will gladly try it.

      Many Thanks.

      • ak6dn's avatar
        ak6dn
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        I don't see why you should not be able to do this. I can do it in Verilog using Quartus 11.0sp1 (and later).

        In the verilog source file:

        reg [0:11] memory [0:MEMSIZE-1] /* synthesis ramstyle = "no_rw_check" */;

        initial $readmemb("meminit.txt", memory, 0, MEMSIZE-1);

        And in the plain text file meminit.txt just 8192 lines with a 12b binary data on each line:

        000000000000
        101100000011
        101100000011
        010110000011
        ...
        000000000000

        This initializes the 8192x12 block ram with the supplied data.

        I am not familiar enough with VHDL to know the exact syntax to use but I would be very surprised if it is not supported in VHDL as well.

        PS:

        Well I guess I gave Altera/Intel too much credit for their VHDL support. Per this old post:

        https://community.intel.com/t5/Programmable-Devices/What-is-VHDL-equivalent-for-Verilog-readmemb-to-initilze-RAM-ROM/td-p/263696

        VHDL memory init is not easy to do in the generic case. Glad I code only in verilog. Never much saw the point to using VHDL.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Could you share the design QAR for investigation? To generate the design QAR, click on Project > Archive Project > Archive


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


    Best regards,

    KhaiY


  • ThomasKendall82's avatar
    ThomasKendall82
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hello,

    I'm sorry for the late response - I've been busy for the last few days.

    I tried to create a simplified example of the problem (as some of you requested) -I re-wrote it based on quartus code templates and the mif file was used correctly.

    After further inspection - I've noticed that my TextIO based initialization function, which should have been for simulation purpose only, did reset the memory to zero even when the TextIO part was not working.

    I overlooked that part untill now because it was supposed to be for simulation only and I was sure it didn't had any effect.

    I think that attribute didn't work because the function already declaired an initial value. (quartus did create a mif file for the zeros the function set to the memory)

    After I've changed that part in the function the attribute worked and all was well.

    Thank you all for your help and advice.