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Altera_Forum's avatar
Altera_Forum
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16 years ago

specify clock settins on quartusII

Hi all,

I'm going to build a system on an Altera FPGA that will incorporates a PLL that generates some clocks fed to internal registers. The PLL will have an input from INCLOCKPLL pin. So my question is:

May I concern only about the input clock timing specifications? Is quartusII able to identify by itself the derived clock properties to performTiming Analysis?

Thanks a lot.

Massi

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Quartus has two timing analyzers. The classic timing analyzer would automatically create clock timing constraints based on your PLL settings. For newer designs (and newer FPGAs) the TimeQuest timing analyzer is the preference (required for new FPGA families). TimeQuest requires that you provide Quartus with a timing analysis script. You can use the TimeQuest GUI to create the script and it can automatically derive the clock constraints from your PLL settings.

    Jake