Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

specify clock settins on quartusII

Hi all, I'm going to build a system on an Altera FPGA that will incorporates a PLL that generates some clocks fed to internal registers. The PLL will have an input from INCLOCKPLL pin. So my quest...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quartus has two timing analyzers. The classic timing analyzer would automatically create clock timing constraints based on your PLL settings. For newer designs (and newer FPGAs) the TimeQuest timing analyzer is the preference (required for new FPGA families). TimeQuest requires that you provide Quartus with a timing analysis script. You can use the TimeQuest GUI to create the script and it can automatically derive the clock constraints from your PLL settings.

Jake