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Altera_Forum
Honored Contributor
Honored ContributorSource synchronous interface on Cyclone III without PLL
Hi, I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into ...
Altera_ForumHonored Contributor
Honored ContributorInstead of explicitly adding lcells, one may also try to specify delays in the timming constrains (set_min_delay and set_max_delay) and see if Quartus is able to produce decent results.
