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Altera_Forum
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16 years ago

Source synchronous interface on Cyclone III without PLL

Hi, I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thanks for the suggestion. So you mean rather than using the megafunction (which isn't supported anyways), just add sequential elements and synthesis attributes to prevent Quartus from blowing them away and using the timing analyzer to get an estimate of the physical delay? I'm not exactly clear how this would be programmable. Could you clarify a bit more? Thanks.

Raphael