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Altera_Forum
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15 years ago

Source synchronous interface on Cyclone III without PLL

Hi, I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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I thought of the I/O delay chains but unfortunately they're not supported in the Cyclone family.

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You can manually add logic cell delay chains to your design, keeping the logic cells by synthesis attributes. Although not that accurate, tt's cheaper than copper delay lines and also programmable.