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Honored Contributor
Honored ContributorSource synchronous interface on Cyclone III without PLL
Hi, I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I thought of the I/O delay chains but unfortunately they're not supported in the Cyclone family. --- Quote End --- You can manually add logic cell delay chains to your design, keeping the logic cells by synthesis attributes. Although not that accurate, tt's cheaper than copper delay lines and also programmable.
