Forum Discussion
gyuunyuu
Contributor
ContributorSource synchronous interface design with Intel FPGAs for high speed ADCs
I need to design a source synchronous interface for high speed ADCs. I have not yet come across any Intel/Altera specific documentation on how to do this. If anything for this exists for Max 10 and C...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
The IP instantiates the DDIO by default.
It uses the clock coming in from ADC (rx_inclock), pass to the PLL to generate faster clock and use it to sample the DDR data at the rate defined by the PLL settings in IP wizard.
For a source synchronous ADC, Data rate will match the Inclock frequency in the PLL settings.
To define the data pins as LVDS, just assign the IO standard as LVDS in Pin planner, and it takes care of the LVDS buffers as well.
Regards.
gyuunyuuThis is well and good. But my question is, why are ALTDDIO_IN, ALTDDIO_OUT and ALTIOBUF not present in the IP catalogue of Max 10?
