Source synchronous interface design with Intel FPGAs for high speed ADCs

Hi,

The IP instantiates the DDIO by default.

It uses the clock coming in from ADC (rx_inclock), pass to the PLL to generate faster clock and use it to sample the DDR data at the rate defined by the PLL settings in IP wizard.

For a source synchronous ADC, Data rate will match the Inclock frequency in the PLL settings.

To define the data pins as LVDS, just assign the IO standard as LVDS in Pin planner, and it takes care of the LVDS buffers as well.

Regards.