Forum Discussion
Occasional ContributorSource Synchronous between 2 Altera FPGA
Hi.
1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html
2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.
Thanks,
Best Regards,
Sheng
Super ContributorHi.
1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html
2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.
Thanks,
Best Regards,
Sheng
