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Altera_Forum's avatar
Altera_Forum
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17 years ago

Sopc sys clk problem

Hi, i use a ddr2 high performance controller and i use the clock he provides altmemddr_sysclk to feed all the components in sopc.

when i compile i get:

Warning: PLL sopc_top:inst|altmemddr:the_altmemddr|altmemddr_controller_phy:altmemddr_controller_phy_inst|altmemddr_phy:alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_sii:altmemddr_phy_alt_mem_phy_sii_inst|altmemddr_phy_alt_mem_phy_clk_reset_sii:clk|altmemddr_phy_alt_mem_phy_pll_sii:pll|altpll:altpll_component|pll" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input

i think is the same clock of above.

With Time Quest i see that i have several path failing because of this clock.

I have setup slack negative -0.6

How should i remove this warning and get things working?

My sopc is working at 150 MHz and the ddr @ 300 MHZ, i would keep this frequencies

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    This is because the clock_source of the PLL in the DDR ip isn't assigned to a pin that can directly drive that PLL.

    It isn't a problem with the SOPC system, it is to do with the constraints on the Quartus project.

    The best thing to do is to find where the PLL is placed in the fitter report, then manually place the input clock to your whole system on a dedicated clock input pin that feeds that PLL.

    Once you have the location of the PLL, look it up in the Stratix II handbook:

    http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf

    and find which pins can drive the inclk port of the PLL (page 13). It will be of the form CLKxxx

    Then you can assign the top level port to that pin in the pin planner.

    Hope this helps
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    To phrase it differently, the reference clock that you provide to the DDR2 controller (which is used as the input clock to the PLL) should come from a dedicated clock input pin on the FPGA. And specifically, it should be a dedicated clock input that can be directly connected to the PLL input.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi, what dedicated means? . I used a 100 MHz clock provided by the board, so i thought was dedicated.

    Now i'm using the other 100 MHz clock provided by the board that is more near to the pll.

    I have set the option Global clock too and the warning gone away.

    Sorry but i'm very new to this
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Getting a clean (low jitter) clock source to the PLL is important for it to get maximum performance, so in addition to the general purpose routing on the chip there are dedicated connections that can be used to drive the PLL without crossing the noisy chip core. For any given PLL, these dedicated connections are only on certain pins.

    In order for Quartus to use the dedicated path a suitable input pin must be used, and there must be a path from that pin to the PLL that the fitter picks.