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Honored Contributor
Honored ContributorSopc sys clk problem
Hi, i use a ddr2 high performance controller and i use the clock he provides altmemddr_sysclk to feed all the components in sopc. when i compile i get: Warning: PLL sopc_top:inst|altmemddr:th...
Altera_ForumHonored Contributor
Honored ContributorGetting a clean (low jitter) clock source to the PLL is important for it to get maximum performance, so in addition to the general purpose routing on the chip there are dedicated connections that can be used to drive the PLL without crossing the noisy chip core. For any given PLL, these dedicated connections are only on certain pins.
In order for Quartus to use the dedicated path a suitable input pin must be used, and there must be a path from that pin to the PLL that the fitter picks.
