Sopc sys clk problem

This is because the clock_source of the PLL in the DDR ip isn't assigned to a pin that can directly drive that PLL.

It isn't a problem with the SOPC system, it is to do with the constraints on the Quartus project.

The best thing to do is to find where the PLL is placed in the fitter report, then manually place the input clock to your whole system on a dedicated clock input pin that feeds that PLL.

Once you have the location of the PLL, look it up in the Stratix II handbook:

http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf

and find which pins can drive the inclk port of the PLL (page 13). It will be of the form CLKxxx

Then you can assign the top level port to that pin in the pin planner.

Hope this helps