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Honored Contributor
Honored ContributorSopc sys clk problem
Hi, i use a ddr2 high performance controller and i use the clock he provides altmemddr_sysclk to feed all the components in sopc. when i compile i get: Warning: PLL sopc_top:inst|altmemddr:th...
Altera_ForumHonored Contributor
Honored ContributorTo phrase it differently, the reference clock that you provide to the DDR2 controller (which is used as the input clock to the PLL) should come from a dedicated clock input pin on the FPGA. And specifically, it should be a dedicated clock input that can be directly connected to the PLL input.
