SOPC Internal Error: std_logic ports/signals must be width 1

There is a bug in v9.0. SOPC builder no longer understands any custom components with a top-level declaration containing any data type besides std_logic and std_logic vector. For instance, if you have an unsigned, signed, or integer port, then attempting to generate your SOPC project generates the above error.

The workaround is to refactor your component to use std_logic and std_logic_vector in the declaration. So, if you had an avalon slave interface with a signal named avs_s1_address you need to change:

avs_s1_address : in unsigned(2 downto 0);

to

avs_s1_address : in std_logic_vector(2 downto 0);

Later in your code you can declare a signal addr like this

signal addr : unsigned(2 downto 0);

and then assign it to the port signal like this

addr <= unsigned(avs_s1_address);

Now you can use the unsigned type addr in your code and SOPC is happy because the port is a std_logic_vector.

great this was working for me!!

passing from std_ulogic to std_logic solved it.

Thanks a lot:)